I am currently a Postdoctoral Research Fellow at the National University of Singapore (NUS), working with Prof. Jiaheng Zhang. I received my Ph.D. under the supervision of Prof. Çetin Kaya Koç at Nanjing University of Aeronautics and Astronautics (NUAA), China.
My research interests mainly involve zero-knowledge proofs, post-quantum cryptography, and elliptic curve cryptography.
Work
Tencent
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Rhino Bird Elite Research Intern
Shenzhen, Guangdong, China
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Summary
Conducted high-impact research as an Elite Intern, specializing in the performance optimization of the SM2 algorithm for critical financial and blockchain platforms.
Highlights
Optimized the SM2 algorithm (Chinese ECC Commercial Standard) on ARMv8-A architecture, improving signing performance by 8.7x and verification by 3.5x compared to OpenSSL.
Leveraged advanced ARMv8-A and Huawei Kunpeng 920 platform expertise to deliver substantial cryptographic performance gains within a fast-paced R&D environment.
Led a critical cooperation project focused on optimizing X/Ed25519 cryptographic implementations for resource-constrained IoT devices, significantly enhancing deployment efficiency and performance.
Highlights
Engineered and optimized X/Ed25519 cryptographic algorithms for ARM Cortex-M3 and 32-bit RISC-V architectures, reducing ROM usage from 70KB (OpenSSL) to 15KB.
Education
Nanjing University of Aeronautics and Astronautics (NUAA)
Nanjing, Jiangsu, China
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Ph.D.Cryptographic EngineeringGrade:
Nanjing University of Aeronautics and Astronautics (NUAA)
Nanjing, Jiangsu, China
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B.S.Software EngineeringGrade: 4.0/5.0 (Top 5%)
Awards
Distinguished Paper Award
Usenix Security
Recognized for groundbreaking research presented at Usenix Security 2024, focusing on 'ENG25519: Faster TLS 1.3 handshake using optimized X25519 and Ed25519.'
Publications
Vectorized Falcon-Sign Implementations using SSE2, AVX2, AVX-512F, NEON, and RVV
IACR TCHES
Falcon, a NTRU-based digital signature algorithm, has been selected by NIST as one of the post-quantum cryptography (PQC) standards. Compared to verification, the signature generation of Falcon is relatively slow. One of the core operations in signature generation is discrete Gaussian sampling, which involves a component known as the BaseSampler. The BaseSampler accounts for up to 30% of the time required for signature generation, making it a significant performance bottleneck. This work aims to address this bottleneck.
We design a vectorized version of the BaseSample and provide optimized implementations across six different instruction sets: SSE2, AVX2, AVX-512F, NEON, RISC-V Vector (RVV), and RV64IM. The AVX2 implementation, for instance, achieves an 8.4x speedup over prior work. Additionally, we optimize the FFT/iFFT operations using RVV and RV64D. For the RVV implementation, we introduce a new method using strided load/store instructions, with 4+4 and 4+5 layer merging strategies for Falcon-{512,1024}, respectively, resulting in a speedup of more than 4x. Finally, we present the results of our optimized implementations across eight different instruction sets for signature generation of Falcon. For instance, our AVX2, AVX- 512F, and RV64GCVB implementations achieve performance improvements of 23%, 36%, and 59%, respectively, for signature generation of Falcon-512.
Optimized Software Implementation of Keccak, Kyber, and Dilithium on RV{32,64}IM{B}{V}.
IACR TCHES
Research on optimizing post-quantum cryptographic algorithms (Keccak, Kyber, Dilithium) for RISC-V architectures, enhancing performance and efficiency.
Revisiting Keccak and Dilithium Implementations on ARMv7-M.
IACR TCHES
Comprehensive analysis and optimization of Keccak and Dilithium cryptographic implementations for ARMv7-M architectures.
ENG25519: Faster TLS 1.3 handshake using optimized X25519 and Ed25519.
Usenix Security
Award-winning paper demonstrating significant acceleration of TLS 1.3 handshake processes through optimized X25519 and Ed25519 implementations.
Yet Another Improvement of Plantard Arithmetic for Faster Kyber on Low-end 32-bit IoT Devices.
IEEE Trans. on Information Forensics and Security
Further enhancements to Plantard Arithmetic to accelerate Kyber implementations, specifically targeting low-end 32-bit IoT devices for improved efficiency.
Efficient Implementation of SM2 for Mobile Devices.
Journal of Electronics
Study on optimizing the SM2 algorithm, a Chinese ECC commercial standard, specifically for performance on mobile device platforms.
Improved Plantard Arithmetic for Lattice-based Cryptography.
IACR TCHES
Advancements in Plantard Arithmetic, contributing to more efficient and secure implementations of lattice-based cryptographic schemes.
Time-Memory Trade-offs for Saber+ on Memory-constrained RISC-V Platform.
IEEE Trans. on Computers
Research exploring and optimizing time-memory trade-offs for the Saber+ cryptographic algorithm on memory-constrained RISC-V platforms.
Efficient and Scalable Sparse Polynomial Multiplication Accelerator for LAC on FPGA.
IEEE ICPADS
Development of an efficient and scalable hardware accelerator for sparse polynomial multiplication, tailored for Lattice-based Cryptography (LAC) on FPGA.
Languages
English
Conversational
Chinese (Mandarin)
Native
Skills
Programming Languages
C, ARM Assembly, RISC-V Assembly, Intel AVX2/AVX-512 Assembly.